1. Field of the Invention
The present invention is related to a method for fabricating a pixel structure, and particularly to a method using less photolithography and etching processes (PEP) to fabricate a pixel structure having a color filter layer.
2. Description of Related Art
With the advantages of high definition, small volume, light weight, low driving voltage, low power consumption and extensive application, the liquid crystal display (LCD) has replaced the cathode ray tube (CRT) as the mainstream of newly developed displays. The conventional LCD panel consists of a color filter substrate have a color filter layer, a thin film transistor (TFT) array substrate and a liquid crystal layer sandwiched therebetween. In order to enhance the resolution of the panel and the aperture ratio of the pixel and to avoid an aligning error when the color filter substrate is jointed to the TFT array substrate, a technique directly integrating a color filter layer to a TFT array substrate (hence, color filter on array, COA) is provided nowadays.
FIGS. 1A through 1G are schematic views showing a flowchart of fabricating a color filter layer on a TFT array. Three pixel structures are illustrated in FIGS. 1A through 1G as a representative example for explanation. First, referring to FIG. 1A, a substrate 10 is provided, and a gate 20 is formed thereon via a first PEP. Afterwards, referring to FIG. 1B, a gate insulator layer 30 is formed on the substrate 10 to cover the gate 20. A channel 40 and an ohmic contact layer 42 are formed on the gate insulator layer 30 over the gate 20 by performing a second PEP. Next, referring to FIG. 1C, a source 50 and a drain 60 are formed over a portion of the channel 40 and a portion of the gate insulator layer 30 by a third PEP. Generally, a material of the channel 40 is amorphous silicon (a-Si) and a material of the ohmic contact layer 42 is an N-type heavily-doped a-Si so that the contact impedance between the channel 40 and the source 50 and the contact impedance between the channel 40 and the drain 60 are reduced. The ohmic contact layer 42 is usually formed by performing N-type doping on a surface of the a-Si.
Referring again to FIG. 1C, the source 50 and the drain 60 extend respectively from two sides of the channel 40 to the gate insulator layer 30 and expose a portion of the channel 40. The gate 20, the channel 40, the source 50 and the drain 60 form a TFT T. Referring to FIG. 1D, a dielectric layer 70 covers the TFT T and a red filter pattern 82 is formed above a portion of the TFT T by a fourth PEP. The red filter pattern 82 has a contact opening H1 and the contact opening H1 is located over the drain 60 of the TFT T corresponding to the red filter pattern 82.
Referring to FIG. 1E, a green filter pattern 84 is formed over a portion of the TFT T by a fifth PEP and a contact opening H2 is formed in the green filter pattern 84. The contact opening H2 is located over the drain 60 of the TFT T corresponding to the green filter pattern 84. Referring to FIG. 1F, a blue filter pattern 86 is formed over a portion of the TFT T by a sixth PEP and a contact opening H3 is formed in the blue filter pattern 86. The contact opening H3 is located over the drain 60 of the TFT T corresponding to the blue filter pattern 86. It is known from FIGS. 1D through 1F that a color filter layer 80 formed by the red filter pattern 82, the green filter pattern 84 and the blue filter pattern 86 is fabricated by three PEPs.
Afterwards, referring to FIG. 1G, the dielectric layer 70 exposed by the contact openings H1, H2 and H3 is removed to expose the drains 60 by an etching process. Then, a pixel electrode 90 is formed on the color filter layer 80 by a seventh PEP. It is known from FIG. 1G that the pixel electrode 90 of each pixel structure is electrically connected to each drain 60 through the contact openings H1, H2 and H3 corresponding thereto respectively. Up until this procedure, direct integration of the color filter layer 80 to the TFT array substrate is substantially completed.
In view of the foregoing, the conventional method requires at least seven PEPs to complete fabrication of the color filter layer on the TFT array substrate. The procedures are complicated and thus require a higher fabricating cost. Moreover, the pixel structure fabricated by at least seven PEPs as described above uses a plurality of masks with different patterns. Since masks are rather expensive, the fabricating cost of the LCD panel cannot be reduced.